1. Field of the Invention
The present invention relates to solid-state image sensing devices, methods for fabricating solid state image sensing devices and an image capture system using the same.
2. Description of Related Art
Integrated circuit image sensors are finding applications in a wide variety of fields, including machine vision, robotics, guidance and navigation, automotive applications, and consumer products such as digital camera and video recorders. Imaging circuits typically include a two dimensional array of photo sensors. Each photo sensor includes one picture element (pixel) of the image. Light energy emitted or reflected from an object impinges upon the array of photo sensors. The light energy is converted by the photo sensors to an electrical signal. Imaging circuitry scans the individual photo sensors to readout the electrical signals. The electrical signals of the image are processed by external circuitry for subsequent display.
Modern metal oxide semiconductor (MOS) design and processing techniques have been developed that provide for the capture of light as charge and the transporting of that charge within active pixel sensors and other structures so as to be accomplished with almost perfect efficiency and accuracy.
One class of solid-state image sensors includes an array of active pixel sensors (APS). An APS is a light sensing device with sensing circuitry inside each pixel. Each active pixel sensor includes a sensing element formed in a semiconductor substrate and capable of converting photons of light into electronic signals. As the photons of light strike the surface of a photoactive region of the solid-state image sensors, free charge carriers are generated and collected. Once collected the charge carriers, often referred to as charge packets or photoelectrons are transferred to output circuitry for processing.
An active pixel sensor also includes one or more active transistors within the pixel itself. The active transistors amplify and buffer the signals generated by the light sensing element to convert the photoelectron to an electronic signal prior to transferring the signal to a common conductor that conducts the signals to an output node.
Active pixel sensor devices are fabricated using processes that are consistent with complementary metal oxide semiconductor (CMOS) processes. Using standard CMOS processes allows many signal processing functions and operation controls to be integrated with an array of active pixel sensors on a single integrated circuit chip.
Refer now to FIGS. 1a-1c for a more detailed discussion of a pinned photo diode active pixel image sensor of the prior art. A substrate 5 heavily doped with a P-type impurity has its surface further doped with a complementary impurity to create a lightly doped P-type epitaxial layer 10. A P-type material is diffused into the surface of the substrate 5 to form the contact diffusions 50 within the P-well diffusion 25a to provide contact of the P-well diffusion 26a to the ground reference voltage. An N-type material is heavily diffused into the surface of the epitaxial layer 10 of the substrate 5 to form the N+ photo diode depletion regions 15a, 15b, and 15c. A P-type material is heavily diffused relatively deeply into the surface of the epitaxial layer 10 of the substrate 5 to form the P-well diffusions 25a and 25b. A P-type material is heavily diffused relatively shallow into the surface of the epitaxial layer 10 of the substrate 5 to form the P-type pinning diffusions 20a and 20b. The P-type pinning diffusions 20a, 20b, and 20c encompass the surface of the N+ photo diode depletion regions 15a, 15b, and 15c and overlap into the surface of the P-well diffusions 25a and 25b. The pinned photodiodes of the image sensors of the illustrate pixels are the N+ photo diode depletion regions 15a, 15b, and 15c and the P-type pinning diffusions 20a, 20b, and 20c respectively.
A gate insulator or thin oxide 95 is placed on the surface of the substrate 5 at appropriate locations above the P-well diffusions 25a, 25b and 25c and polycrystalline silicon is formed on the surface of the thin oxide 95 to form the transfer gates 35a, 35b, and 35c and the reset gates 40a, 40b, and 40c. An N-type material is heavily diffused into the surface of the P-well diffusions 25a and 25b of the substrate 5 to form the floating diffusions 30a, 30b, and 30c and the N+ source/drain regions 45a, 45b, and 45c. The N+ photo diode depletion regions 15a, 15b, and 15c, the transfer gates 35a, 35b, and 35c, and the floating diffusions 30a, 30b, and 30c are a transfer gate switches. The floating diffusions 30a, 30b, and 30c, reset gates 40a, 40b, and 40c and N+ source/drain regions 45a, 45b, and 45c form the reset gate switch.
The transfer gates 35a, 35b, and 35c of the transfer gate switches are connected to a transfer gating signals T_GT 65 and the reset gates 40a, 40b, and 40c of the reset gate switches are connected to the pixel reset signal PIX_RST 70. The N+ source/drain regions 45a, 45b, and 45c are connected to a power supply voltage source VDD. The floating diffusion 30a is connected to the gate of the N-type metal oxide semiconductor (NMOS) transistor 80. The drain of the NMOS transistor 80 is connected to the power supply voltage source VDD and the emitter of the NMOS transistor 80 is connected to the drain of the NMOS transistor 75. The gate of the NMOS transistor 75 is connected to the row select signal 85. The NMOS transistor 75 acts as a source follower to buffer the electrical signal created by the photoelectron charge collected in the floating diffusion 30a. 
The P-type pinning diffusions 20a, 20b, and 20c act rather like a self-biased, internal photogate. The doping levels and implant depths must be carefully controlled to deplete the N+ photo diode depletion regions 15a, 15b, and 15c fully to ensure effective charge transfer from the diode to the floating diffusion. The P-type pinning diffusions 20a, 20b, and 20c pin the potential at the surface to that of the substrate or the ground reference voltage. N+ photo diode depletion regions 15a, 15b, and 15c can tailored such that the depletion region is at the correct depth for efficient optical absorption. The N+ photo diode depletion regions 15a, 15b, and 15c do not have to be so large and the dark current can thus be reduced. The photons that impinge upon the pinned photodiode formed of the P-type pinning diffusion 20a, the N+ photo diode depletion region 15a, and the epitaxial layer 10 are converted to photoelectrons and collected in the N+ photo diode depletion region 15a. At the completion of an integration of the collection of the photoelectrons, the floating diffusion 30a is reset by pulsing the reset gates 40a and then the transfer gate 35a is activated to turn on the transfer gate switch to transfer the collected photoelectrons to the storage node of the floating diffusion 30a. When the collected photoelectrons are retained at the floating diffusion 30a the row select signal 85 is activated to turn on the transistor 75 to gate the pixel output electrical signal PIX_OUT 90 to external circuitry for processing and display. The amplitude of pixel output electrical signal PIX_OUT 90 is indicative of the intensity of the light energy hν or the number of photons 60 absorbed by the pinned photodiode. Once the pixel output electrical signal PIX_OUT 90 is read out the pixel reset signal 70 is activated to turn on the reset gate switch and the N+ photo diode sensor region 15a and the floating diffusion storage node 30a are emptied of the photoelectrons.
As structured, some of the light energy hν 60 impinges upon the transfer gate switch and the reset gate switch and are converted to stray photoelectrons that collect in the floating diffusion storage node 30a. Some of the photoelectrons 62 are generated within the P-type epitaxial layer 10 and have some probability of drifting to the P-well diffusions 25a and 25b. The photoelectrons 63 that drift into the P-well diffusions 25a and 25b then drift to the floating diffusion storage nodes 30a, 30b, and 30c as the photoelectrons 64. The stray photoelectrons 64 then cause noise currents that interfere with the detection of the correct values of light intensity and cause distortion such as blooming and smearing of the image.
Active pixel sensor arrays may be operated in a read-reset mode with a row at a time being read out. This technique has minimum integration time to collect the photons and minimum time for generating a frame, however it may have motion artifacts due to non-simultaneous exposure.
A second type of operation of a CMOS active pixel sensor array is a block access mode. A block of pixels adjacent pixels are readout. This too has minimum integration time for a full block read out. Control for this type of read out is complicated
Typically, a CMOS active pixel sensor array is operated in a rolling shutter mode in which each row of the array is exposed at different instants of time. The non-simultaneous exposure of the pixels can lead to image distortion, for example, when there is relative motion between the imager and the image that is to be captured. Furthermore, although the exposure time generally is defined by the duration for which the pinned photodiode is exposed to the impinging light, floating diffusion regions can continue to collect photoelectrons even after the exposure has terminated. Transfer of such unwanted charges into the sense node can result in image distortion and excess noise. Furthermore, the distortions tend to become more pronounced as the exposure time is reduced.
An alternative to the rolling shutter mode of operation is the snapshot mode with single simultaneous conversion of the photons to the photoelectrons and transfer of the photoelectrons to the floating diffusion storage node. Each pixel is read out one at-a-time readout. Since all pixels are exposed essentially simultaneously, the motion artifact is minimized. However, relatively long integration times (10 msec) precludes the capture of high velocity moving objects without blurring or the motion artifact.
“A Snap-Shot CMOS Active Pixel Imager for Low-Noise, High-Speed Imaging”, Yang, et al., Technical Digest., International Electron Devices Meeting, December 1998, pp.: 45-48, presents the design and performance of a 128×128 snap-shot imager implemented in a standard single-poly CMOS technology. The pixel design and clocking scheme allows the imager to provide high-quality images without motion artifacts at high shutter speeds (<75 μsec, exposure), with low noise (<5 e−), immeasurable image lag, and excellent blooming protection.
“A Numerical Analysis of a CMOS Image Sensor with a Simple Fixed-Pattern-Noise-Reduction Technology”, Yonemoto, et al., IEEE Transactions on Electron Devices, May 2002. Vol. 49, Issue 5, pp.: 746-753, describes a CMOS image sensor with a five-transistor pixel circuit with an L-shaped readout gate for a pinned photodiode and is adequate for rapid charge transfer.
U.S. Pat. No. 6,218,691 Chung, et al. provides an image sensor, including a deep N-region formed on a substrate with a P-type epitaxial region formed within the N-region. An active pixel sensor with a pinned diode is formed within the P-type epitaxial region. A P-well is formed in the P-type epitaxial region and contains the drive and select output transistors for the sensor.
U.S. Pat. No. 6,326,230 (Pain, et al.) describes high speed CMOS imager with motion artifact suppression and anti-blooming. Each pixel of the CMOS imager includes a photoactive region in the semiconductor substrate, a sense node, and a power supply node. A transfer gate is disposed above the surface of the semiconductor substrate. A bias signal applied to the transfer gate sets a potential in a region of the semiconductor substrate between the photoactive region and the sense node for transfer of photoelectrons to the sense node. A reset gate is disposed near the surface of the semiconductor substrate between the photoactive region and the power supply node. A reset signal on the reset gate sets a potential in a region of the semiconductor substrate between the photoactive region and the power supply node for clearing the photoelectrons from the photoactive region after read out of the electrical signal of an image without passing through the sense node.
U.S. Pat. No. 6,521,920 (Abe) provides a solid state image sensor with a primary first-conductivity-type semiconductive region which serves as a charge storage region of a photo-sensing area and a secondary first-conductivity-type semiconductive region for enlarging a charge collecting region of the photo-sensing area.
U.S. Pat. No. 6,737,626 (Bidermann, et al.) teaches an integrated image sensor having a conditioned top silicon oxide layer and/or one or more additional insulating layers/structures to reduce optical and/or electrical noise. The image sensor has one or more insulating structures formed on the substrate and configured to inhibit the flow of electricity between a photoelement and its associated circuitry and/or the pixel and an adjacent pixel in the array.
U.S. Pat. No. 6,885,047 (Shinohara, et al.) describes a solid-state image sensing device. Each pixel of the image sensing device has a photodiode, a first transistor, and a second transistor. A potential barrier is provided under the drain region of the first transistor and the source region and/or the drain region of the second transistor.
U.S. Patent Application 2002/0047086 (Pain) provides a leakage compensated snapshot imager that prevents smear and other problems in a snapshot imager. The area where the imager is formed may be biased in a way that prevents photo carriers including electrons and holes from reaching a storage area.